104/12/23 上機考 NOR

module top; 

wire a, A, b, B, c, C, d, D, NF, F, F1, F2, F3, F4,F5;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nor S1(a, A, A);

nor S2(b, B, B);

nor S3(c, C, C);

nor S4(d, D, D);

nor C1(F1, A,B,c,D);

nor C2(F2, b,C,D);

nor C3(F3, a,C,D);

nor C4(F4, b,c,d); 

nor C5(F5, a,c,d); 

nor o1(NF, F5, F4, F2, F3, F1);

nor o2(F, NF, NF);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

上機考(二) NOR

module top; 

wire a, A, b, B, c, C, d, D, NF, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nor S1(a, A, A);

nor S2(b, B, B);

nor S3(c, C, C);

nor S4(d, D, D);

nor C1(F4, a ,C , D);

nor C2(F2, A, B, d);

nor C3(F3, b, C, D);

nor C4(F1, c, d); 

nor o1(NF, F4, F2, F3, F1);

nor o2(F, NF, NF);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

上機考(二) NAND

module top; 

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand S1(a, A, B);

nand S2(b, B, B);

nand S3(c, C, C);

nand S4(d, D, D);

nand C1(F4, A ,c , d);

nand C2(F2, a, b, D);

nand C3(F3, B, c, d);

nand C4(F1, C, D); 

nand o1(F, F4, F2, F3, F1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

上機考(一)AND/OR/NOT

module top; 

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

not S1(a, A);

not S2(b, B);

not S3(c, C);

not S4(d, D);

and C1(F4, A ,c , d);

and C2(F2, a, b, D);

and C3(F3, B, c, d);

and C4(F1, C, D); 

or o1(F, F4, F2, F3, F1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

三位元全加法器 行為

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

assign{c_out,sum}=a+b+c_in;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c; 

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

三位元全加法器 結構

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

xor g1(s1, a, b);

xor g2(sum, s1, c_in);

and g3(c1, a,b);

and g4(c2, s1, c_in) ;

xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

一位元全加法器 卡諾圖

module top;

wire Cin,A,B,Cout,Sum;

system_clock #400 clock1(Cin); 

system_clock #200 clock2(A);

system_clock #100 clock3(B);

adder1 M1(Cout, Sum, A, B, Cin);

endmodule

module adder1(Cout, Sum, A, B, Cin);

output Cout,Sum;

input A,B,Cin;

and I1 (AandB, A, B);

xor I2 (AxorB, A, B);

and I3 (And1, AxorB, Cin);

or I4 (Cout, AandB, And1);

xor I5 (Sum, AxorB, Cin);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule