2+2位元=4位元

module top; 

wire [3:0]OUT, A, B;

wire SEL;

system_clock #12800 clock1(A[3]); 

system_clock #6400 clock2(A[2]); 

system_clock #3200 clock3(A[1]);

system_clock #1600 clock4(A[0]);

system_clock #800 clock5(B[3]);

system_clock #400 clock6(B[2]);

system_clock #200 clock7(B[1]);

system_clock #100 clock8(B[0]);

system_clock #25600 clock7(SEL);

mux2 m1(OUT[1:0],A[1:0],B[1:0],SEL);

mux2 m2(OUT[3:2],A[3:2],B[3:2],SEL);

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

 if($time>25600)$stop;

endmodule