module top; 

wire A1,A2,A3,SEL,B1,B2,B3,M1,M2,M3,M4,M5,M6,M7;

system_clock #12800 clock4(SEL);

system_clock #6400 clock1(A1);

system_clock #3200 clock2(A2);

system_clock #1600 clock3(A3);

system_clock #800 clock5(B1);

system_clock #400 clock6(B2);

system_clock #200 clock7(B3);

and a1(M1,A1,SEL);

and a2(M2,A2,SEL);

and a3(M3,A3,SEL);

not a7(M7,SEL);

and a4(M4,B1,M7);

and a5(M5,B2,M7);

and a6(M6,B3,M7);

or  c1(OUT1,M1,M4);

or  c2(OUT2,M2,M5);

or  c3(OUT3,M3,M6);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>10000000)$stop; 

endmodule