AND 邏輯在路

module top;

wire A,B,C,D,out1,out2,out3;
system_clock#800 clock(A);
system_clock#400 clock(B);
system_clock#200 clock(C);
system_clock#100 clock(D);

and a1(out1,A,B);
and a2(out2,D,C);
and a3(out3,out2,out1);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule