2+2位元=4位元

module top; 

wire [3:0]OUT, A, B;

wire SEL;

system_clock #12800 clock1(A[3]); 

system_clock #6400 clock2(A[2]); 

system_clock #3200 clock3(A[1]);

system_clock #1600 clock4(A[0]);

system_clock #800 clock5(B[3]);

system_clock #400 clock6(B[2]);

system_clock #200 clock7(B[1]);

system_clock #100 clock8(B[0]);

system_clock #25600 clock7(SEL);

mux2 m1(OUT[1:0],A[1:0],B[1:0],SEL);

mux2 m2(OUT[3:2],A[3:2],B[3:2],SEL);

endmodule 

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

 if($time>25600)$stop;

endmodule 

1位元加上2位元組成3位元

module top;

wire [2:0]OUT, A, B;

wire SEL;

system_clock #3200 clock1(A[2]);

system_clock #1600 clock2(A[1]);

system_clock #800 clock3(A[0]);

system_clock #400 clock4(B[2]);

system_clock #200 clock5(B[1]);

system_clock #100 clock6(B[0]);

system_clock #6400 clock7(SEL);

mux m1(OUT[0],A[0],B[0],SEL);

mux2 m2(OUT[2:1],A[2:1],B[2:1],SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

 if($time>6400)$stop;

endmodule

module top; 

wire A1,A2,A3,SEL,B1,B2,B3,M1,M2,M3,M4,M5,M6,M7;

system_clock #12800 clock4(SEL);

system_clock #6400 clock1(A1);

system_clock #3200 clock2(A2);

system_clock #1600 clock3(A3);

system_clock #800 clock5(B1);

system_clock #400 clock6(B2);

system_clock #200 clock7(B3);

and a1(M1,A1,SEL);

and a2(M2,A2,SEL);

and a3(M3,A3,SEL);

not a7(M7,SEL);

and a4(M4,B1,M7);

and a5(M5,B2,M7);

and a6(M6,B3,M7);

or  c1(OUT1,M1,M4);

or  c2(OUT2,M2,M5);

or  c3(OUT3,M3,M6);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>10000000)$stop; 

endmodule

module top;

wire A1, B1,SEL,A0,B0 ,OUT1,OUT0;
system_clock #1600 clock1(A1);
system_clock #800 clock2(B1);
system_clock #400 clock3(SEL);
system_clock #200 clock4(A0);
system_clock #100 clock5(B0);

mux S1(OUT1,A1,B1,SEL);
mux S2(OUT0,A0,B0,SEL);

多公器 1

odule top;

wire A1, A0, B1, B2, OUT1, OUT2, OUT4, OUT5, OUT6, OUT7, OUT8;
system_clock #100 clock1(B0);
system_clock #200 clock2(B1);
system_clock #400 clock3(SEL);
system_clock #800 clock4(A0);
system_clock #1600 clock5(A1);

and a1(OUT4, A1, SEL);
and a2(OUT5, A0, SEL);
not n1(OUT6, SEL);
and a3(OUT7, OUT6, B1);
and a4(OUT8, OUT6, B0);
or o1(OUT1, OUT4, OUT7);
or o2(OUT2, OUT5, OUT8);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

10/7

module top;

wire A,B,C,D,E,OUT1,OUT2,OUT3,OUT4,OUT5,F;

system_clock#1600 clock(A);
system_clock#800 clock(B);
system_clock#400 clock(C);
system_clock#200 clock(D);
system_clock#100 clock(E);

not a1(OUT1,A);
and a2(OUT2,OUT1,B);
or a3(OUT3,C,D);
not a4(OUT4,OUT3);
and a5(OUT5,OUT4,E);
or a6(F,OUT2,OUT5);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

AND 邏輯在路

module top;

wire A,B,C,D,out1,out2,out3;
system_clock#800 clock(A);
system_clock#400 clock(B);
system_clock#200 clock(C);
system_clock#100 clock(D);

and a1(out1,A,B);
and a2(out2,D,C);
and a3(out3,out2,out1);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule